VHDL

A strongly typed HDL, popular in Europe, aerospace and defence.

Advanced

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
  port (clk, rst : in std_logic;
        count    : out unsigned(3 downto 0));
end entity;

architecture rtl of counter is
  signal c : unsigned(3 downto 0) := (others => '0');
begin
  process (clk) begin
    if rising_edge(clk) then
      if rst = '1' then c <= (others => '0');
      else c <= c + 1;
      end if;
    end if;
  end process;
  count <= c;
end architecture;

An entity declares the ports; an architecture describes the behaviour. VHDL is more verbose than Verilog but its strict typing catches many mistakes at compile time.

Spotted a mistake or want to add detail? Suggest an improvement — Content Contributors' edits are reviewed by editors before they go live.

Discussion (0)