Logic Families

TTL and CMOS logic levels, noise margins, fan-out and level shifting.

Intermediate

Family	Supply	$V_{IL}$ max	$V_{IH}$ min
TTL (74LS)	5 V	0.8 V	2.0 V
CMOS (74HC) at 5 V	2–6 V	1.5 V	3.5 V
74HCT	5 V	0.8 V	2.0 V (TTL-compatible inputs)
3.3 V LVCMOS	3.3 V	0.8 V	2.0 V

Noise margin: $NM_H = V_{OH} - V_{IH}$ , $NM_L = V_{IL} - V_{OL}$ .

Connecting 5 V outputs to a 3.3 V chip that isn't 5 V-tolerant can damage it. Use a level shifter (a resistor divider for slow one-way signals, a MOSFET circuit like the BSS138 for I2C, or ICs such as the TXS0108).

Sub-topics (2)

Pull-Up and Pull-Down Resistors

Resistors that hold an input at a defined level when nothing is driving it.

Beginner♥ 0🔖 0💬 0

Tri-State and Open-Drain Outputs

Outputs that can disconnect from a line, allowing several devices to share a bus.

Intermediate♥ 0🔖 0💬 0

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Sub-topics (2)

Pull-Up and Pull-Down Resistors

Tri-State and Open-Drain Outputs

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