Verilog

A C-like HDL for modelling and synthesising digital logic.

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module counter (
    input  wire       clk,
    input  wire       rst,
    output reg  [3:0] count
);
    always @(posedge clk) begin
        if (rst) count <= 4'd0;
        else     count <= count + 1;
    end
endmodule

Key ideas: modules with ports, wire (connections) and reg (stored values), assign for combinational logic and always @(posedge clk) for sequential logic. Test with a testbench in a simulator such as Icarus Verilog or ModelSim.

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Blocking vs Non-Blocking Assignments

Use = for combinational logic and <= for sequential (clocked) logic in Verilog.

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Sub-topics (1)

Blocking vs Non-Blocking Assignments

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