Latches and Flip-Flops

• SR latch — two cross-coupled NOR/NAND gates; S sets, R resets (S = R = 1 is invalid).
• D latch — transparent while enable is high.
• D flip-flop — captures D only on the clock edge: $Q_{next} = D$.
• JK flip-flop — like SR, but J = K = 1 toggles.
• T flip-flop — toggles when T = 1: $Q_{next} = T \oplus Q$.

Timing parameters: setup time and hold time (D must be stable around the edge) and clock-to-Q delay. Violating them can cause metastability.