Blocking vs Non-Blocking Assignments

Use = for combinational logic and <= for sequential (clocked) logic in Verilog.

Advanced

Blocking = updates immediately, in order — like software.
Non-blocking <= evaluates all right-hand sides first, then updates together at the end of the time step — exactly like flip-flops sharing a clock edge.

always @(posedge clk) begin
    b <= a;    // a shift register: both update "at the same time"
    c <= b;
end

With = instead, c would receive the new value of b, collapsing the shift register. Rule of thumb: <= in clocked always blocks, = in combinational always @(*) blocks — and never mix them in one block.

Spotted a mistake or want to add detail? Suggest an improvement — Content Contributors' edits are reviewed by editors before they go live.

Discussion (0)