Microcontroller Architecture

CPU core, buses, memory map, clock system and Harvard vs von Neumann designs.

Intermediate

Harvard architecture (AVR, PIC): separate buses for program and data memory — fetch and data access at the same time.
von Neumann: a shared bus for both.
ARM Cortex-M uses a modified Harvard design within a single memory map: flash, SRAM and peripheral registers all have addresses.

The clock system (internal RC oscillator, external crystal, PLL) sets the speed. RISC cores execute simple instructions in one or a few cycles. Other blocks: interrupt controller (NVIC), DMA controller, watchdog timer and debug interface.

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