Phase-Locked Loop

A PLL has a phase detector, a loop filter and a VCO. The detector compares the VCO's phase with the reference and steers the VCO until they match.

With a divide-by-N counter in the feedback path:

$f_{out} = N \cdot f_{ref}$

So a 25 MHz crystal can produce a stable 1 GHz CPU clock (N = 40). PLLs also demodulate FM, recover clocks from serial data and generate the channels in every radio.