RTL Coding Guidelines
Write HDL that synthesises predictably: one clock per process, no latches by accident, registered outputs, clear FSMs.
Intermediate
Simulate what you synthesise — avoid constructs that behave differently in each.
Spotted a mistake or want to add detail? Suggest an improvement — Content Contributors' edits are reviewed by editors before they go live.
Discussion (0)
Sign in or join free to ask questions and discuss this topic.