HDL Tools
Vendor suites, open-source simulators and synthesis tools, verification frameworks and waveform viewers.
This is an overview — pick a sub-topic below.
Sub-topics (24)
AMD Vivado
AMD (Xilinx) FPGA design suite: synthesis, implementation, IP integrator, timing analysis and hardware manager.
AMD Vitis
AMD's software and acceleration platform: embedded software for Zynq/MicroBlaze, HLS and AI engines.
Intel Quartus Prime
Altera/Intel FPGA design software for Cyclone, MAX, Arria, Stratix and Agilex devices.
Microchip Libero SoC
Design suite for Microchip PolarFire and IGLOO FPGAs.
Lattice Radiant and Diamond
Lattice's FPGA tools for its small, low-power FPGAs (iCE40, ECP5, CertusPro-NX).
Gowin EDA
Tools for low-cost Gowin FPGAs used in Tang Nano boards.
Icarus Verilog
A free Verilog simulator — easy to install for learning.
Verilator
A very fast open-source simulator that compiles (System)Verilog into C++.
GHDL
Open-source VHDL simulator and synthesis front-end (with Yosys plugin).
QuestaSim and ModelSim
Siemens' industry-standard HDL simulators; ModelSim/Questa starter editions come with FPGA tools.
Xcelium and VCS
Cadence and Synopsys commercial simulators for large ASIC verification.
Vivado Simulator
The simulator built into Vivado (XSim) supporting Verilog, SystemVerilog and VHDL.
Yosys
Open-source synthesis suite for Verilog — the heart of open FPGA and ASIC flows.
nextpnr
Open-source FPGA place-and-route for Lattice iCE40/ECP5, Gowin and others.
OpenLane
An automated open-source RTL-to-GDSII ASIC flow built on OpenROAD and the SkyWater 130 nm PDK.
OpenROAD
Open-source physical design tools: floorplanning, placement, CTS, routing and timing.
Surelog
A SystemVerilog parser and elaborator producing the UHDM data model for other tools.
Verible
Google's SystemVerilog parser, linter and formatter.
svlint
A configurable SystemVerilog linter written in Rust.
cocotb
Write HDL testbenches in Python with async coroutines; works with Icarus, Verilator, GHDL and commercial simulators.
OSVVM
Open Source VHDL Verification Methodology: constrained random, coverage and scoreboards in VHDL.
UVVM
Universal VHDL Verification Methodology — structured testbenches and verification components in VHDL.
SymbiYosys
Front-end for formal verification with Yosys and open solvers.
GTKWave
The free waveform viewer for VCD/FST/GHW files.
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