Hardware Description Languages and HDL Frameworks
The languages and generators used to describe hardware — from Verilog and VHDL to Python and Scala-based tools. Verilog and VHDL have their own pages earlier in this subject.
This is an overview — pick a sub-topic below.
Sub-topics (14)
SystemVerilog
Verilog's superset (IEEE 1800) for design and verification: `logic`, `always_ff`/`always_comb`, interfaces, packages, classes, constraints and assertions.
VHDL-AMS
VHDL extended for analog and mixed-signal modelling (IEEE 1076.1).
SystemC
A C++ library for system-level modelling and simulation of hardware (IEEE 1666).
Bluespec SystemVerilog
A high-level HDL based on guarded atomic rules; the compiler generates scheduling logic.
Chisel
A hardware construction language embedded in Scala that generates Verilog.
SpinalHDL
A Scala-based HDL generating VHDL/Verilog, with built-in clock-domain safety checks.
Amaranth HDL
A Python-based HDL (formerly nMigen) with a clean syntax and simulator.
MyHDL
Write and simulate hardware in Python, then convert to Verilog/VHDL.
Migen and nMigen
Python toolboxes for building hardware; Migen underlies LiteX SoC builder, nMigen became Amaranth.
PyRTL
A simple Python RTL framework designed for teaching and research.
Clash
A Haskell-based functional HDL compiling to VHDL/Verilog.
Lava
An early family of Haskell-embedded hardware description libraries.
TL-Verilog
Transaction-Level Verilog: describes pipelines with timing abstraction; Makerchip runs it in the browser.
e Language and Specman
A verification language (IEEE 1647) for constrained-random testbenches, run by Cadence Specman.
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