RTL Design and Verification
Writing synthesisable register-transfer-level code and proving it works. Blocking vs non-blocking assignments have their own page under Verilog.
This is an overview — pick a sub-topic below.
Sub-topics (17)
RTL Coding Guidelines
Write HDL that synthesises predictably: one clock per process, no latches by accident, registered outputs, clear FSMs.
Combinational always Blocks
`always @(*)` / `always_comb` blocks model logic without memory.
Sequential always Blocks
`always @(posedge clk)` / `always_ff` blocks model flip-flops.
Continuous Assignments
`assign y = a & b;` drives a net continuously — simple combinational logic and wiring.
Parameters and Generics
Make modules configurable: `parameter WIDTH = 8` (Verilog) / `generic (WIDTH : integer := 8)` (VHDL).
SystemVerilog Interfaces
Bundle related signals (e.g. an AXI bus) into one port with modports for each side.
Packages
Share types, constants and functions across files (SystemVerilog `package`, VHDL `package`).
Generate Blocks
Create repeated or conditional hardware at elaboration time.
Assertions
SystemVerilog Assertions (SVA) and PSL check temporal properties during simulation and formal proofs.
Functional Coverage
Measure which scenarios the tests actually exercised (covergroups, coverpoints, crosses).
Testbenches
HDL code that drives inputs and checks outputs of the design under test.
Constrained-Random Verification
Generate random but legal stimulus with constraints to find corner cases humans miss.
UVM
Universal Verification Methodology: a standard SystemVerilog class library for reusable testbenches.
Formal Verification
Prove mathematically that properties hold for all inputs, not just tested ones.
HDL Linting
Static checks for latches, width mismatches, multiple drivers and style issues.
CDC Analysis
Tools that find unsafe clock-domain crossings structurally.
Synthesis Constraints
Tell tools about clocks, I/O timing and exceptions (SDC/XDC).
Spotted a mistake or want to add detail? Suggest an improvement — Content Contributors' edits are reviewed by editors before they go live.
Discussion (0)
Sign in or join free to ask questions and discuss this topic.