FPGA and ASIC Design
How FPGAs work and the steps from RTL to a programmed FPGA or manufactured chip.
This is an overview — pick a sub-topic below.
Sub-topics (18)
FPGA Architecture
Configurable logic blocks (LUTs + flip-flops), routing, block RAM, DSP slices, clock managers and I/O.
ASIC Design Flow
Specification → RTL → verification → synthesis → floorplan → place and route → timing/power signoff → DRC/LVS → tape-out.
Synthesis
Convert RTL into a netlist of gates (ASIC) or LUTs/flip-flops (FPGA).
Place and Route
Position each cell on the chip and connect them with routing while meeting timing.
Static Timing Analysis
Check timing on every path without simulation, across process/voltage/temperature corners.
Floorplanning
Decide where major blocks, I/O and macros go on the die or FPGA.
Clock-Tree Synthesis
Build a balanced buffer network that delivers the clock to every flip-flop with low skew.
Power Analysis
Estimate static (leakage) and dynamic power ($P = \alpha C V^2 f$).
Area Optimization
Use fewer gates/LUTs: resource sharing, simpler arithmetic, right-sized widths, using DSP blocks and RAMs.
Timing Closure
Iterating until all timing constraints are met.
Design for Test (DFT)
Add structures that make manufactured chips testable: scan chains, BIST, boundary scan.
Scan Chains
Connect flip-flops into shift registers in test mode to load and read internal states.
BIST
Built-In Self-Test: on-chip pattern generators and checkers (e.g. memory BIST).
JTAG Boundary Scan in Chips
Boundary-scan cells on each pin let testers control and observe I/O via JTAG.
Bitstream Generation
The final FPGA step: produce the configuration file that programs the device.
FPGA IP Cores
Pre-built blocks: memory controllers, PCIe, Ethernet MACs, soft CPUs (MicroBlaze, Nios V), FFTs.
High-Level Synthesis (HLS)
Generate RTL from C/C++ with pragmas for pipelining and parallelism.
SoC Integration
Connect CPUs, memories, accelerators and peripherals with standard buses (AXI, AHB, APB, Wishbone).
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