Skip to content
UPEEC

Design for Test (DFT)

Add structures that make manufactured chips testable: scan chains, BIST, boundary scan.

Expert
Comments 0

Testing finds manufacturing defects, not design bugs.

Spotted a mistake or want to add detail? Suggest an improvement — Content Contributors' edits are reviewed by editors before they go live.

Discussion (0)

Sign in or join free to ask questions and discuss this topic.